The present invention relates to digital signal processing in general, and in particular to methods and apparatus for implementing a receiver filter with logarithmic coefficient multiplication.
Specialized computer processors dedicated for digital signal processing (DSP) applications are well known in the art and are widely used for a variety of purposes. These processors are particularly adapted to perform complex mathematical operations on signals. Such operations may include matrix multiplication, matrix-inversion, Fast Fourier Transforms (FFT), auto and cross correlation, Discrete Cosine Transforms (DCT), polynomial equations, and difference equations in general, such as those used to approximate Infinite Impulse Response (IIR) and Finite Impulse Response (FIR) filters.
DSP processors vary considerably in design and function. In general, the more complex the mathematical operations that a DSP processor is requited to perform, the more complex is its architecture. Simplifying the complexity of these mathematical operations will often result in the reduction of DSP processing hardware and software and an increase in processing speed. One such simplification approach targets the filtering of digital signals which requires extensive multiplication operations involving the addition of intermediate numerical results.
By way of example, consider a receiver filter where samples of received data di are filtered by a FIR filter with coefficients ci. The filter output yt is given according to the formula:       y    k    =            ∑              j        =        0                    N        -        1              ⁢          xe2x80x83        ⁢                  d                  k          -          j                    ⁢              c        j            
The complexity of the filters due to the large number of multiplications required, N operations for each sample. Each multiplication operation is a complex multiplication operation as di and ci are usually complex numbers, thus requiring four real-number multiplication operations. For example, the multiplication of two complex numbers x=xR+x1 and y=yR+y1 is as follows:
xy=(xR+jxI)(yR+jyI)=xRyRxe2x88x92xjyI+j(xIyR+xRyI)
The multiplication of two real numbers may also be performed using the following relation;   ab  =      {                                                      sign              ⁡                              (                a                )                                      ⁢                          sign              ⁡                              (                b                )                                      ⁢                          exp              ⁡                              [                                                      ln                    ⁢                                          "LeftBracketingBar"                      α                      "RightBracketingBar"                                                        +                                      ln                    ⁢                                          "LeftBracketingBar"                      b                      "RightBracketingBar"                                                                      ]                                                                                        if              ⁢                              xe2x80x83                            ⁢              a                        ≠                          0              ⁢                              xe2x80x83                            ⁢              and              ⁢                              xe2x80x83                            ⁢              b                        ≠            0                                                0                                      otherwise            ⁢                          xe2x80x83                                          
The multiplication operation is much more complex than addition, thus addition is performed instead of multiplication. While this requires performing a logarithmic conversion of the result, an efficiency is realized due to the compression effect of the logarithmic operation. The quantization noise subsequent to the logarithmic operation is proportional to the signal, thus making is possible to decrease the number of quantization bits subsequent to the logarithmic operation.
Thus, the multiplications required for the filtering of digital signals may be simplified by supplanting the addition of intermediate numerical results with the addition of the logarithms of numbers to be added. An inverse logarithm or antilog operation may then be performed on the summation of the logarithms to yield the desired multiplication result.
The present invention seeks to provide improved methods and apparatus for implementing a receiver filter with logarithmic coefficient multiplication.
There is thus provided in accordance with a preferred embodiment of the present invention a method of filtering a signal, the method including the steps of sampling an analog input signal, thereby providing a plurality of digital complex input signal samples the each of the samples indicates a sign and a magnitude, for each of the complex input signal samples demultiplexing the complex input signal sample into a first sign component and a first magnitude component, performing a logarithmic conversion on the first magnitude component, thereby resulting in a first logarithmic value, demultiplexing a complex coefficient into a second sign component and a second magnitude component, performing a logarithmic conversion on the second magnitude component, thereby resulting in a second logarithmic value, adding the first and second logarithmic values, thereby resulting in a third logarithmic value, performing an antilog conversion on the third logarithmic value, thereby resulting in an antilog value, XORing the first and second sign components, thereby resulting in an output sign, providing the antilog value as an output signal component having the output sign where both of the first and second magnitude components have nonzero values, and providing an output signal component having a zero value where either of the first and second magnitude components has a zero value, and summing the output signal components, thereby providing a filtered signal.
Further in accordance with a preferred embodiment of the present invention the method includes the step of storing the plurality of complex input signal samples in a sample storage.
Still further in accordance with a preferred embodiment of the present invention the method includes the step of storing the complex coefficient in a coefficient storage.
There is also provided in accordance with a preferred embodiment of the present invention a method of filtering a signal, the method including the steps of sampling an analog input signal, thereby providing a plurality of digital complex input signal samples the each of the samples indicates a sign and a magnitude, for each of the complex input signal samples demultiplexing the complex input signal sample into a first sign component and a first magnitude component, performing a logarithmic conversion on the first magnitude component, thereby resulting in a first logarithmic value, demultiplexing a complex coefficient logarithmic value into a second sign component and a second magnitude component, the second magnitude component now referred to as a second logarithmic value, adding the first and second logarithmic values, thereby resulting in a third logarithmic value, performing an antilog conversion on the third logarithmic value, thereby resulting in an antilog value, XORing the first and second sign components, thereby resulting in an output sign, providing the analog value as an output signal component having the output sign where both of the first and second magnitude components have nonzero values, and providing au output signal component having a zero value where either of the first and second magnitude components has a zero value, and suing the output signal components, thereby providing a filtered signal.
Further in accordance with a preferred embodiment of the present invention the method includes the step of storing the plurality of complex input signal samples in a sample storage.
Still further in accordance with a preferred embodiment of the present invention the method includes the step of storing the complex coefficient logarithmic value in a coefficient storage.
Additionally in accordance with a preferred embodiment of the present invention the method includes the step of representing a zero value complex coefficient as the complex coefficient logarithmic value with a fixed combination of bits that is uniquely representative of the zero value.
There is additionally provided in accordance with a preferred embodiment of the present invention a signal filter including sampling means operative to receive a down-converted analog complex input signal including in-phase (I) and quadrature-phase (Q) signal channels and sample the analog input signal, thereby providing a plurality of digital complex input signal samples the each of the samples indicates a sign and a magnitude, first, second, third, and fourth real multipliers, each real multiplier including demultiplexing means operative to demultiplex each of the complex input signal samples into a first sign component and a first magnitude component and a corresponding complex coefficient into a second sign component and a second magnitude component, logarithmic conversion means operative to perform a logarithmic conversion on the first magnitude component, thereby resulting in a first logarithmic value and a logarithmic conversion on the second magnitude component, thereby resulting in a second logarithmic value, a first adder operative to add the first and second logarithmic values, thereby resulting in a third logarithmic value, antilog conversion means operative to perform an antilog conversion on the third logarithmic value, there resulting in an antilog value, XORing means operative to XOR the first and second sign components, thereby resulting in an output sign, zero detection means operative to detect a zero value for either of the first and second magnitude components and provide a zero value indicator, and multiplexing means operative to receive the output sign from the XORing apparatus, receive the zero value indicator from the zero detection apparatus, receive the antilog value from the antilog conversion apparatus, provide the antilog value as an output signal component having the output sign where both of the first and second magnitude components have nonzero values, and provide an output signal component having a zero value where either of the first and second magnitude components has a zero value, a second adder operative to sum the output signal components from the first and second real multipliers, a third adder operative to sum the output signal components from the third and fourth real multipliers, and a fourth adder operative to sum the summed output signal components from the second and third adders, thereby providing a filtered signal.
There is also provided in accordance with a preferred embodiment of the present invention a signal filter including sampling means operative to receive a down-converted analog complex input signal including in-phase (I) and quadrature-phase (Q) signal channels and sample the analog input signal, thereby providing a plurality of digital complex input signal samples the each of the samples indicates a sign and a magnitude, first, second, third, and fourth real multipliers, each real multiplier including demultiplexing means operative to demultiplex each of the complex input signal samples into a first sign component and a first magnitude component and a corresponding complex coefficient logarithmic value into a second sign component and a second magnitude component, the second magnitude component now referred to as a second logarithmic value, logarithmic conversion means operative to perform a logarithmic conversion on the first magnitude component, thereby resulting in a first logarithmic value, a first adder operative to add the first and second logarithmic values, thereby resulting in a third logarithmic value, antilog conversion means operative to perform an antilog conversion on the third logarithmic value, thereby resulting in an antilog value, XORing means operative to XOR the first and second sign components, thereby resulting in an output sign, zero detection means operative to detect a zero value for either of the first and second magnitude components and provide a zero value indicator, and multiplexing means operative to receive the output sign from the XORing apparatus, receive the zero value indicator from the zero detection apparatus, receive the antilog value from the antilog conversion apparatus, provide the antilog value as an output signal component having the output sign where both of the first and second magnitude components have nonzero values, and provide an output signal component having a zero value where either of the first and second magnitude components has a zero value, a second adder operative to sum the output signal components from the first and second real multipliers, a third adder operative to sum the output signal components from the third and fourth real multipliers, and a four adder operative to sum the summed output signal components from the second and third adders, thereby providing a filtered signal.